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Module 2 — CPU Architecture

Learning Objectives

After completing this module, you should be able to explain:

  • What is a CPU?
  • What are the internal components of a CPU?
  • How does the CPU execute a program?
  • What is the Fetch–Decode–Execute cycle?
  • What is the role of registers?
  • What are ARM and x86 architectures?
  • How does the OS interact with the CPU?

1. What is a CPU?

CPU stands for Central Processing Unit.
It is the brain of the computer. Every instruction from your C/C++ program eventually reaches the CPU as machine code.

For example:

int a = 10;
int b = 20;
int c = a + b;

The CPU does not understand C.
The compiler converts it into machine instructions such as:

LOAD R1, a
LOAD R2, b
ADD  R3, R1, R2
STORE c, R3

The CPU executes these one instruction at a time.

2. CPU Internal Organization

CPU

Control Unit
ALU
Registers
Cache (L1)
↓
RAM

Every modern CPU mainly consists of

  • Control Unit
  • ALU
  • Registers
  • Cache
  • Internal buses

3. CPU Components

Control Unit (CU)

The Control Unit acts like a manager.
Responsibilities:

  • Fetch instructions
  • Decode instructions
  • Send control signals
  • Coordinate execution
  • Control memory access

Without the Control Unit,
nothing happens.

Example

Instruction:
ADD R1,R2

Control Unit tells

Read Register R1
↓
Read Register R2
↓
Enable ALU
↓
Store result

The ALU does not decide what to do.
The Control Unit tells it.

Arithmetic Logic Unit (ALU)

The ALU performs

  • Arithmetic: +, -, *, /, %
  • Logical: AND, OR, NOT, XOR, SHIFT
  • Comparison: >, <, ==, !=

Example

10 + 20
ALU output
30

Registers

Registers are tiny memories inside the CPU.
They are the fastest storage available.

Example

RAM
→
Register
→
ALU
→
Register
→
RAM

Later we'll study each register individually.

Cache

Cache stores recently used data.

CPU
↓
L1 Cache
↓
L2 Cache
↓
L3 Cache
↓
RAM

Without cache,
CPU would wait hundreds of clock cycles for RAM.

4. CPU Instruction Cycle

Every CPU repeats the same cycle millions or billions of times per second.

Fetch
→
Decode
→
Execute
→
Write Back
→
Repeat

Step 1 — Fetch

CPU fetches the next instruction.

RAM
→
MOV R1,100
→
CPU

Step 2 — Decode

Control Unit understands
MOV
means Move data.

Step 3 — Execute

ALU executes
ADD, SUB, SHIFT, LOAD, STORE

Step 4 — Write Back

Result stored
Register or RAM

Example

a=10
b=20
c=a+b

Execution

Fetch LOAD a
↓
Decode
↓
Execute
↓
Register
↓
Fetch LOAD b
↓
Register
↓
Fetch ADD
↓
ALU
↓
30
↓
Store

5. Fetch–Decode–Execute Diagram

RAM
↓
Instruction
↓
FETCH
↓
DECODE
↓
EXECUTE
↓
STORE RESULT

This cycle never stops while the CPU is running.

6. CPU Clock

CPU works according to a clock.

Example
3 GHz
means
3 Billion clock cycles/second

Each instruction takes one or more clock cycles.

Example

  • ADD: 1 Cycle
  • Multiply: 3 Cycles
  • Division: 15 Cycles

(Not exact; varies by CPU.)

7. Single-Core vs Multi-Core

Single Core

CPU
|
Core 1

Multi-Core

CPU
|
Core 1
Core 2
Core 3
Core 4

Each core executes instructions independently.
Operating systems schedule different processes or threads onto these cores.

8. Pipeline (High-Level)

Modern CPUs overlap instruction execution.

Without Pipeline

Instruction1
→
Finish
→
Instruction2
→
Finish
→
Instruction3

With Pipeline

Cycle 1 Fetch I1
Cycle 2 Decode I1 Fetch I2
Cycle 3 Execute I1 Decode I2 Fetch I3

Multiple instructions are in progress simultaneously, improving throughput.

9. ARM vs x86

ARM x86
RISC CISC
Simple instructions Complex instructions
Lower power Higher power
Mobile Desktop/Server
Automotive PC
Efficient Feature rich

Why ARM dominates automotive?

  • Lower power
  • Smaller silicon area
  • Better thermal characteristics
  • High performance per watt
  • Widely licensed for embedded SoCs

Your ADAS platforms are likely based on ARM Cortex-A or Cortex-R families.

10. Embedded Example

Suppose
Camera captures image.

Camera
↓
DDR Memory
↓
CPU Fetch
↓
ISP
↓
Image Processing
↓
Display

CPU executes

Noise Reduction
→
Edge Detection
→
Object Detection
→
Display

Each stage is a sequence of machine instructions.

11. OS Interaction with CPU

Operating System
↓
Scheduler
↓
CPU
↓
Execute Process
↓
Timer Interrupt
↓
Scheduler
↓
Next Process

The OS never "runs" independently; it runs on the CPU just like applications, but with higher privileges (kernel mode).

12. Real-Life Analogy

Imagine a restaurant.

  • Chef = CPU
  • Recipe = Program
  • Ingredients = Memory
  • Kitchen Table = Registers
  • Knife = ALU
  • Manager = Control Unit
  • Orders = Instructions

The chef repeatedly:

  1. Reads the next recipe step (Fetch)
  2. Understands it (Decode)
  3. Performs it (Execute)
  4. Places the result on the plate (Write Back)

13. Interview Questions

Beginner

  • What is a CPU?
  • What are the main CPU components?
  • What is the role of the ALU?
  • What is the Control Unit?
  • What is a register?

Intermediate

  • Explain the Fetch–Decode–Execute cycle.
  • Why are registers faster than RAM?
  • Why is cache needed?
  • How does a multi-core CPU improve performance?
  • What is instruction pipelining?

Senior

  • Explain how the CPU executes int c = a + b;.
  • What happens when the CPU encounters a branch instruction?
  • How does pipelining affect performance?
  • Why does ARM consume less power than x86?
  • How does the OS use timer interrupts to implement multitasking?

Common Mistakes

  • ❌ Thinking the ALU controls the CPU. (The Control Unit orchestrates execution.)
  • ❌ Assuming the CPU executes C code directly. (It executes machine instructions.)
  • ❌ Believing all instructions take one clock cycle. (Execution time varies.)
  • ❌ Assuming multi-core CPUs automatically make every program faster. (The software must have parallel work to benefit.)

Summary

The CPU is responsible for executing machine instructions. It repeatedly performs the Fetch–Decode–Execute cycle using the Control Unit, ALU, registers, and caches. Understanding this internal flow is essential before learning about context switching, interrupts, memory management, and scheduling.

Mini Quiz

  1. Why can't the CPU execute C code directly?
  2. What is the role of the Control Unit?
  3. What is the difference between the ALU and the Control Unit?
  4. Why are registers faster than RAM?
  5. Explain the Fetch–Decode–Execute cycle in your own words.
  6. Why is ARM commonly used in embedded and automotive systems?
  7. Why doesn't adding more CPU cores always speed up a single-threaded application?
Knowledge Check

Concept Mastery Assessment — Module 02

Verify your conceptual understanding with 12 targeted technical assessment questions. Instant feedback and explanations are provided for every choice.

Question 1 of 12
Which functional unit within the CPU performs binary addition, bitwise masking, and comparisons?
Explanation
The ALU handles integer arithmetic operations (+, -, *) and bitwise logical manipulations (AND, OR, XOR, shifts).
Question 2 of 12
What is the primary difference between RISC and CISC instruction set architectures?
Explanation
RISC (Reduced Instruction Set Computer) focuses on load/store architectures with simple, fixed-length instructions, whereas CISC provides rich, complex instructions.
Question 3 of 12
In a modern CPU, what is the role of the micro-operation (uOp) engine?
Explanation
Modern CISC cores (like x86) decode complex instructions into smaller RISC-like micro-ops (uOps) dispatched to out-of-order execution ports.
Question 4 of 12
Which register holds the memory address of the next machine instruction scheduled to be fetched?
Explanation
The Program Counter (PC or RIP in x86_64) continually points to the memory address of the next instruction to fetch.
Question 5 of 12
What is the function of the Memory Address Register (MAR)?
Explanation
The MAR interfaces directly with the address bus, specifying the physical or virtual address target for memory access.
Question 6 of 12
What is the function of the Memory Data Register (MDR) / Memory Buffer Register (MBR)?
Explanation
The MDR acts as a two-way electrical buffer holding data read from memory or waiting to be written across the data bus.
Question 7 of 12
What type of instruction set architecture uses a dedicated 'load/store' design where arithmetic instructions operate strictly on CPU registers?
Explanation
RISC processors mandate load/store architectures: ALU operations can only access registers, requiring explicit load and store instructions for memory.
Question 8 of 12
What is the purpose of the CPU status/flags register (e.g., EFLAGS/RFLAGS)?
Explanation
The flags register stores status bits (ZF, CF, SF, OF) indicating the outcome of arithmetic and logic operations, enabling conditional jumps.
Question 9 of 12
What is the role of the CPU clock generator in synchronous digital processors?
Explanation
The clock signal regulates the exact rhythm at which internal state registers latch data and control signals propagate.
Question 10 of 12
What occurs when an unhandled hardware interrupt pin asserts during CPU execution?
Explanation
Hardware interrupts cause the CPU to complete the current instruction, push execution context, and branch to the vector address for the ISR.
Question 11 of 12
What is out-of-order execution (OoOE) in modern superscalar processors?
Explanation
OoOE dynamic scheduling executes non-dependent instructions while waiting for slow memory loads, committing results in-order via a reorder buffer.
Question 12 of 12
What architectural component in a modern superscalar CPU is responsible for ensuring instructions retire and commit architectural state in program order?
Explanation
The Reorder Buffer tracks in-flight out-of-order instructions and ensures they commit to the register file and memory in strict original program order.
0 / 12 (0%)
Great job! Review the concepts above and proceed when ready.
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