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Module 3 — CPU Registers

Learning Objectives

After completing this module, you should be able to answer:

  • What is a register?
  • Why are registers the fastest memory?
  • How many registers does a CPU have?
  • What are General Purpose Registers?
  • What is Program Counter?
  • What is Stack Pointer?
  • What is Instruction Register?
  • What is Flag Register?
  • What is Link Register (ARM)?
  • What is Frame Pointer?
  • How are registers used during function calls?
  • How does the OS save registers during a context switch?

1. What is a Register?

A register is a very small storage location inside the CPU.
It stores:

  • Data
  • Addresses
  • Instructions
  • CPU state

Think of registers as the CPU's working desk.
RAM is like a bookshelf.
SSD is like a warehouse.
The CPU prefers to keep frequently used values on its desk instead of walking to the bookshelf every time.

Memory Hierarchy

Fastest

Registers
↓
L1 Cache
↓
L2 Cache
↓
L3 Cache
↓
RAM
↓
SSD
↓
Hard Disk

Slowest

Why are Registers Fast?

Registers are physically inside the CPU core.

CPU

Registers
ALU
Control Unit
Cache
↓
RAM → Outside CPU

There is almost no distance for data to travel.
Access time is typically one CPU cycle.
RAM may take tens to hundreds of cycles.

Register Sizes

Different CPUs have different register widths.

  • 8-bit CPU: Register = 8 bits
  • 16-bit CPU: Register = 16 bits
  • 32-bit CPU: Register = 32 bits
  • 64-bit CPU: Register = 64 bits

Example

32-bit register:

00000000 00000000
00000000 00001010

Stores 10

Types of Registers

The CPU contains different registers for different purposes.

CPU

General Registers
Program Counter
Stack Pointer
Instruction Register
Status Register
Frame Pointer
Link Register (ARM)
Floating Point Registers
Vector Registers

We'll focus on the most important ones first.

2. General Purpose Registers (GPR)

These are the CPU's "scratchpad."
They store:

  • Variables
  • Intermediate results
  • Function arguments
  • Addresses

Example

int a = 10;
int b = 20;
int c = a + b;

Machine execution

LOAD R1,a
LOAD R2,b
ADD R3,R1,R2
STORE c,R3

Registers

  • R1 = 10
  • R2 = 20
  • R3 = 30

The ALU performs operations on register values.

ARM Registers

ARM Cortex typically has:

R0
R1
R2
...
R12
SP
LR
PC

Where R0-R12 are General Registers.

x86 Registers

RAX
RBX
RCX
RDX
RSI
RDI
RBP
RSP
RIP

Each has traditional roles, but modern compilers use them flexibly.

3. Program Counter (PC)

One of the most important registers.
The Program Counter stores the address of the next instruction to execute.

Example Program

AddressInstruction
1000MOV R1,#10
1004ADD R2,R1,#20
1008SUB R3,R2,#5
  • Initially: PC = 1000
  • CPU fetches: MOV
  • After execution: PC = 1004
  • Next: PC = 1008
  • And so on.

Visualization

1000: Instruction1
1004: Instruction2
1008: Instruction3
↑ PC

The Program Counter keeps moving through the program.

Branch Example

Suppose if(a>10)

The PC no longer goes to the next sequential instruction. Instead:

PC
↓
Jump
↓
3000

This is how loops, if, switch, and function calls work.

4. Stack Pointer (SP)

The Stack Pointer points to the top of the stack.

Memory
Local Variable
Return Address
Function Argument
Stack Pointer

Every function call changes the Stack Pointer.

Example

void fun()
{
   int a;
}

Entering the function

Stack grows
↓
SP moves

Returning

Stack shrinks
↓
SP moves back

Stack Growth

On most architectures, the stack grows downward.

High Address
Stack
↓
↓
↓
SP
Low Address

5. Instruction Register (IR)

The Instruction Register stores the current instruction being executed.

Suppose memory contains ADD R1,R2

Flow

RAM
↓
Instruction Register
↓
Decode
↓
ALU

The IR acts like the CPU's "currently open page."

6. Status Register (Flags Register)

The CPU needs to know the result of operations.

Example: 5-5=0

How does it know the result is zero? Through status flags.

Typical Flags

  • Zero Flag (Z)
  • Carry Flag (C)
  • Negative Flag (N)
  • Overflow Flag (V)

Example: 10-10
Result: 0
The CPU sets: Zero Flag = 1

Then if(result==0) can use that flag to decide the branch.

7. Link Register (LR) — ARM

ARM has a special register called the Link Register.
Purpose: Store the return address during a function call.

Example

main()
↓
fun()

Before jumping to fun():

LR
→
Stores
→
Return Address

When fun() finishes, BX LR returns to the caller.
This reduces stack accesses for simple function calls.

8. Frame Pointer (FP)

Frame Pointer identifies the base of the current function's stack frame.

Function
Arguments
Return Address
Saved Registers
Local Variables
SP
FP

Debuggers rely heavily on the Frame Pointer to reconstruct call stacks.

9. Register Usage During Function Calls

Example

int add(int a, int b)
{
   return a+b;
}

ARM calling convention

a
→
R0
b
→
R1
Result
→
R0

Small arguments stay in registers.
Large structures are passed via memory.

10. Context Switching

This is where registers become critical for the OS.
Suppose Process A is running.

Registers: PC, SP, R0, R1, R2, ...

A timer interrupt occurs.
The OS must save all CPU state.

PCB
↓
Save
PC
SP
Registers
Flags

Then restore Process B's saved state.

PCB
↓
Restore
↓
Registers
↓
Continue

This is why a process can resume exactly where it stopped.

Embedded Example

In an ADAS camera pipeline:

Camera Interrupt
↓
CPU
↓
ISR
↓
Scheduler
↓
Task Switch
↓
Restore Registers
↓
Continue Image Processing

The task resumes because its registers (PC, SP, GPRs, flags) were saved and restored.

ARM vs x86 Register Comparison

ARM x86
R0-R12 RAX, RBX, RCX, RDX...
SP RSP
LR Return address stored on stack (typically)
PC RIP
CPSR RFLAGS

ARM's dedicated Link Register is a notable difference.

Interview Questions

Beginner

  • What is a register?
  • Why are registers faster than RAM?
  • What is the Program Counter?
  • What is the Stack Pointer?
  • What is the Instruction Register?

Intermediate

  • Explain how a function call uses registers.
  • Why does the Stack Pointer change?
  • What are CPU flags?
  • Why is the Program Counter important?
  • What is the purpose of the Frame Pointer?

Senior

  • How does the OS perform a context switch?
  • Which registers must be saved during an interrupt?
  • How does ARM use the Link Register?
  • Explain register allocation by the compiler.
  • Why are calling conventions important?

Common Mistakes

  • ❌ Thinking registers are part of RAM.
  • ❌ Assuming the Program Counter points to the current instruction (it generally points to the next instruction to fetch, though exact behavior depends on the architecture and pipeline).
  • ❌ Believing the Stack Pointer always increases. On most CPUs, it decreases as the stack grows.
  • ❌ Assuming all variables remain in registers. The compiler spills values to memory when registers are insufficient or when required.

Summary

Registers are the CPU's fastest storage and hold the immediate execution state of a program. Specialized registers such as the Program Counter, Stack Pointer, Instruction Register, and Status Register enable instruction execution, function calls, branching, interrupts, and multitasking. Operating systems rely on saving and restoring these registers during context switches, making them fundamental to process and thread management.

Mini Quiz

  1. Why are registers faster than cache and RAM?
  2. What does the Program Counter store?
  3. Why is the Stack Pointer needed?
  4. What information does the Status Register contain?
  5. What is the purpose of ARM's Link Register?
  6. Which registers must an operating system preserve during a context switch?
  7. How does the Frame Pointer help a debugger?
Knowledge Check

Concept Mastery Assessment — Module 03

Verify your conceptual understanding with 12 targeted technical assessment questions. Instant feedback and explanations are provided for every choice.

Question 1 of 12
Why are CPU registers the fastest storage tier in the entire memory hierarchy?
Explanation
Registers reside directly on the execution silicon, constructed from high-speed static latches, allowing access within fractions of a clock cycle.
Question 2 of 12
In the x86-64 architecture, what is the width of the general-purpose registers (RAX, RBX, RCX, etc.)?
Explanation
x86-64 provides sixteen 64-bit general-purpose registers: RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, and R8 through R15.
Question 3 of 12
If you write to the 32-bit register 'EAX' in an x86-64 binary, what happens to the upper 32 bits of the 64-bit 'RAX' register?
Explanation
In x86-64, writes to 32-bit register destinations (e.g., EAX, EDX) automatically zero-extend into the upper 32 bits of the corresponding 64-bit register.
Question 4 of 12
In standard x86-64 System V AMD64 ABI (Linux/UNIX), which register is conventionally used to return integer or pointer return values from functions?
Explanation
Under the System V AMD64 ABI, scalar return values (integers, pointers) are returned in RAX (and RDX for 128-bit values).
Question 5 of 12
Which register pair in x86 architecture is traditionally specialized for source and destination indexing in memory string operations?
Explanation
RSI (Source Index) and RDI (Destination Index) were historically designed for block memory operations (movs, cmps) and now serve as primary ABI argument registers.
Question 6 of 12
What flag in the EFLAGS/RFLAGS register is asserted when an arithmetic operation results in an unsigned number that exceeds the register bit capacity?
Explanation
The Carry Flag (CF) detects unsigned arithmetic overflow or borrow conditions, whereas the Overflow Flag (OF) detects signed two's complement overflow.
Question 7 of 12
What is the distinction between 'caller-saved' (volatile) and 'callee-saved' (non-volatile) registers in compiler calling conventions?
Explanation
If a caller needs values in caller-saved registers after a function call, it must save them. Callee-saved registers must be preserved by the callee before use.
Question 8 of 12
In the System V AMD64 ABI (Linux), what are the first six registers used to pass integer/pointer arguments to a function?
Explanation
The System V AMD64 ABI passes the first 6 integer/pointer parameters in registers RDI, RSI, RDX, RCX, R8, and R9.
Question 9 of 12
Which x86 control register contains the physical base address of the top-level page table directory (PML4 or CR3)?
Explanation
Control Register 3 (CR3) holds the physical base address of the page directory or page map level 4 (PML4) table used for address translation.
Question 10 of 12
What information does Control Register 2 (CR2) hold upon a page fault exception on x86 processors?
Explanation
When a page fault (#PF) occurs, the CPU hardware automatically loads CR2 with the 32-bit or 64-bit linear address that attempted the invalid memory access.
Question 11 of 12
What is the function of the Instruction Pointer (RIP) register in x86-64?
Explanation
RIP points to the memory location of the next machine code instruction that will be fetched by the instruction pipeline.
Question 12 of 12
What role do Segment Registers (CS, DS, SS, ES, FS, GS) play in 64-bit Long Mode on modern Linux?
Explanation
x86-64 Long Mode uses a flat memory model, ignoring CS/DS/SS base addresses, while FS and GS are retained for Thread-Local Storage and kernel structures.
0 / 12 (0%)
Great job! Review the concepts above and proceed when ready.
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