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Module 6 — Instruction Register (IR) & Fetch–Decode–Execute Cycle

Learning Objectives

By the end of this module, you should be able to explain:

  • What is the Instruction Register (IR)?
  • Why is it needed?
  • What happens after the Program Counter points to an instruction?
  • How does the CPU understand an instruction?
  • What does the Control Unit do?
  • What are micro-operations?
  • How do instructions move through the CPU?
  • How does this relate to Operating Systems?

1. What is an Instruction?

Suppose we write

int c = a + b;

The CPU cannot understand C.
Compiler converts it into machine instructions.

Example

LOAD R1, [a]
LOAD R2, [b]
ADD R3, R1, R2
STORE [c], R3

Each line above is an instruction.

What is an Instruction?

An instruction tells the CPU

Perform one operation.

Examples

  • ADD
  • SUB
  • LOAD
  • STORE
  • MOV
  • JMP
  • CALL
  • RET
  • CMP

Everything the CPU does is made from these basic instructions.

2. Instruction Register (IR)

The Instruction Register stores the instruction currently being executed.
Think of it as the CPU's current working instruction.

Example

Memory

1000LOAD R1,a
1004LOAD R2,b
1008ADD
1012STORE

Program Counter
PC =1000

CPU fetches
LOAD R1,a

Instruction Register now contains

IR
↓
LOAD R1,a

Only after the instruction is copied into the IR does the CPU decode and execute it.

Visualization

RAM
↓
Instruction
↓
Instruction Register
↓
Control Unit
↓
ALU
↓
Registers

3. Why Do We Need an Instruction Register?

Suppose CPU directly executed instructions from RAM.

Problem
RAM is much slower than the CPU.

Instead

RAM
↓
IR
↓
Execution

The IR provides a stable copy of the current instruction while the CPU decodes and executes it.

4. Fetch–Decode–Execute Cycle

Every processor repeatedly performs:

Fetch
→
Decode
→
Execute
→
Write Back
→
Next Instruction

This happens billions of times every second.

5. Step 1 — Fetch

Suppose
PC =1000

CPU performs
Memory[1000]

Returns
ADD R1,R2

Instruction copied into IR.
PC updated
1004

Diagram

PC
↓
RAM
↓
Instruction
↓
IR

Step 2 — Decode

Instruction Register
ADD R1,R2

Control Unit asks
What instruction is this?

Answer
ADD

Operands?
R1
R2

Destination?
R1

Decoded successfully.

Step 3 — Execute

Control Unit enables

  • ALU
  • Registers
  • Internal buses

Execution

R1=10
R2=20
↓
ALU
↓
30

Step 4 — Write Back

Result stored
R1=30

Now
Program Counter already points to the next instruction.
Cycle repeats.

Complete Execution

Suppose

LOAD R1,a
LOAD R2,b
ADD
STORE

Execution

Fetch LOAD
↓
Decode
↓
Execute
↓
Fetch LOAD
↓
Decode
↓
Execute
↓
Fetch ADD
↓
Decode
↓
Execute
↓
Fetch STORE
↓
Decode
↓
Execute

This never stops while the CPU is running.

6. What Does the Control Unit Actually Do?

Many engineers think the ALU controls the CPU.
Wrong.
The Control Unit is the brain inside the CPU.

Responsibilities

  • Reads IR
  • Decodes instruction
  • Generates control signals
  • Enables registers
  • Starts ALU
  • Reads memory
  • Writes memory
  • Updates PC

Without the Control Unit
nothing executes.

Example

Instruction
ADD R1,R2

Control Unit internally performs

Read Register R1
↓
Read Register R2
↓
Enable ALU
↓
Perform Addition
↓
Store Result
↓
Update Flags

7. Micro-Operations

A single instruction is actually broken into many smaller hardware steps called micro-operations.

Example

Instruction
LOAD R1,[2000]

Internally

PC → Address Bus
↓
Memory Read
↓
Memory → Data Bus
↓
Data → IR
↓
Decode
↓
Address Calculation
↓
Memory Read
↓
Register Write

One assembly instruction often becomes multiple micro-operations.

8. Machine Instruction Format

An instruction contains fields.

Example
ADD R1,R2

Internally

Opcode Destination Register Source Register
0001 001 010

Meaning

Opcode
↓
ADD
Destination
↓
R1
Source
↓
R2

The CPU decodes these bit fields.

9. Example Execution

Suppose
Registers
R1=5
R2=8

Instruction
ADD R1,R2

Execution

Fetch
↓
IR
↓
Decode
↓
ALU
↓
13
↓
Store
↓
R1=13

10. Real Embedded Example

Suppose
Camera frame arrives.

Driver

Camera Interrupt
↓
ISR
↓
Read Register
↓
Read DMA Buffer
↓
Process Image
↓
Return

Every instruction inside the ISR follows the same Fetch–Decode–Execute cycle.
Whether it's a simple MOV or a complex algorithm, the CPU still executes one machine instruction at a time (or multiple simultaneously in a pipelined processor, as we'll see later).

11. Relation to Operating Systems

The OS itself is just another program executing instructions.

Scheduler

Fetch
↓
Decode
↓
Execute

Context Switch

Fetch
↓
Decode
↓
Save Registers
↓
Restore Registers

Interrupt Handler

Fetch
↓
Decode
↓
ISR

The CPU doesn't know it's running an operating system—it simply executes instructions according to the current privilege level and execution state.

12. ARM Example

Instruction
ADD R0,R1,R2

Meaning
R0 = R1 + R2

Execution

Fetch
↓
Decode
↓
ALU
↓
R0 Updated

x86 Example

Instruction
ADD EAX,EBX

Meaning
EAX=EAX+EBX

Same CPU cycle

Fetch
↓
Decode
↓
Execute

13. Complete CPU Data Flow

Program Counter
|
V
Memory
|
V
Instruction Register
|
V
Control Unit
|
V
V
Registers
ALU
|
|
|
V
Write Back
|
V
Update Program Counter

This diagram captures the essence of instruction execution.

14. Why Is This Important?

Every OS concept builds on this:

  • Process execution
  • Thread execution
  • Interrupts
  • Scheduling
  • Context Switching
  • Virtual Memory
  • Device Drivers

Without the Fetch–Decode–Execute cycle, nothing in the system runs.

Interview Questions

Beginner

  • What is the Instruction Register?
  • What is an instruction?
  • Explain the Fetch–Decode–Execute cycle.
  • What is the role of the Control Unit?

Intermediate

  • What happens after the Program Counter identifies an instruction?
  • Why do we need an Instruction Register?
  • Explain the execution of an ADD instruction.
  • What is an opcode?

Senior

  • Explain how a CPU executes one machine instruction internally.
  • What are micro-operations?
  • How does the Control Unit generate control signals?
  • Why are instructions broken into micro-operations?
  • How does the Fetch–Decode–Execute cycle interact with pipelining?

Common Mistakes

  • ❌ Thinking the CPU executes C statements directly. It executes machine instructions.
  • ❌ Believing the Instruction Register stores an entire program. It stores only the current instruction.
  • ❌ Assuming one assembly instruction always maps to one hardware action. Many instructions require multiple micro-operations.
  • ❌ Thinking the ALU controls execution. The Control Unit orchestrates the entire process.

Summary

The Instruction Register temporarily holds the instruction currently being processed by the CPU. The processor repeatedly performs the Fetch–Decode–Execute cycle: it fetches the instruction pointed to by the Program Counter, stores it in the Instruction Register, decodes it using the Control Unit, executes it using the ALU and registers, writes back the result, and proceeds to the next instruction. This cycle underpins every program, operating system, interrupt handler, and device driver.

Mini Quiz

  1. Why is an Instruction Register needed?
  2. What are the four major stages of the instruction cycle?
  3. What is the role of the Control Unit?
  4. What is an opcode?
  5. Why can a single assembly instruction require multiple micro-operations?
  6. Does the CPU distinguish between application code and operating system code during execution?
  7. What happens immediately after an instruction is fetched?
Knowledge Check

Concept Mastery Assessment — Module 06

Verify your conceptual understanding with 12 targeted technical assessment questions. Instant feedback and explanations are provided for every choice.

Question 1 of 12
What is the primary function of the Instruction Register (IR)?
Explanation
The Instruction Register holds the machine code instruction fetched from memory so the Control Unit can decode opcode and operand fields.
Question 2 of 12
Which phase of the machine cycle translates binary machine opcode bits into specific hardware control signals?
Explanation
During the decode stage, the Control Unit examines the opcode bits in the Instruction Register and activates internal micro-operation control lines.
Question 3 of 12
What is the role of the microcode ROM in complex CISC instruction decoders?
Explanation
CISC architectures use microcode ROM to sequence complex instructions into simpler micro-operations that drive internal ALU and register paths.
Question 4 of 12
What component of a machine instruction specifies the operation to be performed (e.g., ADD, SUB, MOV)?
Explanation
The opcode specifies the machine operation to execute, while operand specifiers identify the target registers or memory locations.
Question 5 of 12
In a non-pipelined processor, if Fetch takes 2ns, Decode takes 1ns, Execute takes 3ns, Memory takes 2ns, and Write-Back takes 1ns, what is the total instruction latency?
Explanation
In a non-pipelined single instruction cycle, total latency is the direct sum of all stage durations: 2 + 1 + 3 + 2 + 1 = 9 ns.
Question 6 of 12
What addressing mode specifies the operand value directly within the machine instruction itself?
Explanation
Immediate addressing embeds the operand constant directly inside the instruction bytes (e.g., 'mov eax, 42').
Question 7 of 12
What occurs when the instruction decoder encounters an undefined or illegal opcode bit pattern?
Explanation
Invalid opcodes trigger an illegal instruction hardware exception (#UD on x86), which the OS kernel catches and handles by sending SIGILL to the process.
Question 8 of 12
What is the difference between hardwired control units and microprogrammed control units?
Explanation
Hardwired control uses dedicated logic gates offering higher clock speeds, while microprogrammed control interprets instructions via microcode ROM.
Question 9 of 12
What happens during the 'Memory Access' stage of the classical 5-stage RISC instruction cycle?
Explanation
In the MEM stage, load and store instructions access data cache/memory using the effective address computed by the ALU in the EX stage.
Question 10 of 12
Why do modern x86 processors translate variable-length CISC instructions into fixed-size micro-operations (uOps)?
Explanation
Decomposing variable-length x86 instructions into uniform uOps allows cores to exploit RISC pipelining, out-of-order scheduling, and parallel execution units.
Question 11 of 12
What is an 'effective address' in computer architecture?
Explanation
Effective address calculation resolves complex addressing modes into a single memory offset before issuing the read/write request.
Question 12 of 12
What hardware bus transaction occurs during the Fetch stage of instruction execution?
Explanation
Fetch places the PC value onto the address bus, issues a memory read command, and latches the instruction byte stream into the Instruction Register.
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